Constructing and interfacing an individually addressable electrode array with ≥ 10000 electrodes runs into pin count and routing problems. There is room on the chemical microprocessor for a small FPGA chip with ca 80-200 pins for specific I/O (larger pin counts are available on larger FPGAs but still not enough). This inevitably means that many electrodes must be controlled by a single signal. The major design issue is then to ensure minimum functional cross-talk between those electrodes controlled by a common signal. Both the placement of electrodes for optimal use and the decisions about patterns of commonly driven electrodes are resulting critical design criteria. In order to implement the electrode designs for rapid prototyping, originally only a single gold layer was available, but (in a custom development together with caesar) this has now been extended to allow twin-layer routing by gold layers on silicon substrates. The minimum widths of such plated wires (and of interlayer vias) limit the density of routing in such a twin-layer implementation.
So the goals are to provide a layout of a large but limited number of electrodes showing:
(i) sufficient fine-grained resolution for local control,
(ii) sufficient global connectivity to programmably transport (and separate) molecules across the device, and
(iii) sufficient independence of local and global action to avoid functional cross-talk through common drive channels.