PACE REPORT

The environment and physics of the simulations

In principle more or less every aspect of the physical environment can be adjusted or implemented via the execution of special instructions.

The biggest issue with these special physics-emulation instructions is the number of bits needed to specify a replicating program. The more instructions needed, to specify details which could  be handled otherwise by the physics, the larger the search space is. Sequence-space sizes larger than 2²⁴ are already to big for being exhaustively searched by current day computers. Also, utilizing the dynamic properties of all the none-replicative micro-controllers will not solve the problem. It might be the case that a cascade of 10 different micro-controllers in a network each doing some particular job will in the end result in a replicator-system. But it might also be that this cascade of 10 different micro-controllers actually tries to avoid the development of a replicator because the intermediate steps are more sensitive to perturbations for the system than doing nothing - indeed this is what almost always happens. Robustness is one of the most severe selection pressures in these dynamical systems. Avoiding disturbance is much more rewarded than trying to change something which of course in the beginning might be bad for the whole system. So far, this striving for becoming robust has been the major bottleneck for explaining how non-replicators eventually would evolve or better develop into enzyme-like replication systems. Intriguing enough, this need for simplification - minimizing the number of bits needed - could be best accomplished by assuming physical behavior and removing the according physics' specifying instructions from the instruction-set. Thus, it was possible to come to an instruction-set which still is universal, man-programmable and which only needs 22 significant bits in the minimum-replicator case, see table 5 (left part). With these 22 bits evolution from scratch is possible though still not trivial.

Specific versus unspecific attachment

What turns out to be an important physical property is the distinction between specific attachment (a communication shall only be realized with a specified other micro-controller) or any unspecific connection, see [48]. This distinction is needed because otherwise micro-controllers either simply replicate their genomes (programs) in small cycles without being able to proliferate the sequences or they are replicating everything and become vulnerable to information dilution. Specificity can be realized in several ways: either with a fixed-recognition-site and an additional wild-carding, see classifier systems and building-block hypothesis [24] or a composition of the recognition-site from smaller modules. Both variants allow to adjust specificity and both variants have been studied. A structural drawback of the wild-carding approach is the length of the recognition-site. This means that one recognition site can at most have the length of the width of the cargo-part, which in the simplest case, is two bits. This problem is not existent with the modular-approach where it is easy to concatenate many modules (cargo-parts of the Site-instructions) to one large recognition-site.

Containment or avoiding the parasites

Containment can be done in two aspects: either to introduce space, in our case the containers connected like beads on a ring, or, in sequence-space to communicate only via specific recognition. Both aspects have beneficial consequences in reducing the number of foreign machines to communicate with but exert the drawback of not letting new information, resources and energy diffusing into the container or the occupied sequence-space domain. A vesicle which has no channel-proteins protects the inside pretty well from perturbations from the outside but makes it also extremely difficult to exchange educts and products of chemical reactions in the vesicle. This dichotomy was the rational for the open-container-concept. A further point is the need to somehow specify the compartment in the heritable part of the information constituting the replication system. This can be a huge amount of information which has to be stabilized against perturbation events and which is not available right from the beginning, thus it would have to be created de novo by evolution.

Recognition sites and protection

From a computer-science point of view software with many existing recognition sites per program should be benign for evolution because contact can be made easily. On the other hand, exactly this high connectivity might be a curse, because everyone can interfere. Only one recognition site per program turned out to be a good choice for the moment. For example, molecules in the RNA-world [26] have to be small and probably will not be able to maintain several recognition sites per molecule. Similar with protection, in chemistry it is quite standard to work with protecting groups. It is easy to implement protection in the micro-controller, e.g. if the PF2-bit (see table 4) of a micro-controller is set then this micro-controller becomes invisible. Unfortunately, being protected also hinders others to do the necessary changes. Protection without control of the protection is an evolutionary dead-end. An important problem concerning specificity is the specificity of recognition sites. In [48] a special wild-carding system was used but handling the wild-cards is computationally expensive. Furthermore, wild-cards are somehow difficult when mapping them to biochemistry. In this work a more promising approach was considered, the concatenation of Site-instructions to form a larger recognition-site. This makes handling easy, solves the problem of specificity and is biologically more convenient. If no Site-instructions precede, for example a Load-instruction, then only the bits in the cargo-part of the Load-instruction are used for recognizing a neighboring micro-controller. With several Site-instructions before Load and the cargo-part not pointing to one of the attachment-slots the bits of the cargo-part are appended to the already existing virtual recognition-site, giving a larger recognition-site. If the Load-instruction, see table 2, wants to access the program section of a neighboring micro-controller (address 0 or 1) then a micro-controller is searched for with the appropriate virtual recognition-site, address 0 or 1 bits are not appended to this virtual recognition-site. If no Site-instructions are preceding the Load-instruction a micro-controller is chosen at random - yielding unspecific recognition. It is assured that this neighboring micro-controller is not already attached to a different slot. Self-attachment is not possible. If no appropriate micro-controller was found nothing is done and the next instruction is executed. A small difference holds for the write-instruction (Store to address 0 or 1). If no other micro-controller was found the program is stopped, because finding a suitable micro-controller at a later stage lacks synchronization anyway. This attempt to reduce computer utilization is arguable and can of course be changed at a later stage. Another solution would be to search for the next smaller recognition-site but this again will be postponed to future research.

Bi-molecular versus tri-molecular reactions and the instruction-pointer counter (IPC)

This point is probably the most controversial one: in nature bi-molecular reactions are abundant. Only rarely tri-molecular chemical reactions will occur. And thus the experiments before have been of the bi-molecular type, [48]. In general, replication requires three different algorithmic steps: 1) take the information to be replicated, e.g. a nucleotide, 2) process it somehow, e.g. via a synthetase and 3) store it at the destination place, e.g. create the peptide-bond. Translated into computer-science language this means a Load-operation, writing the data into a local register (ACCU) and exert a subsequent Store-operation. Usually Load- and Store-operations require a register-address as well. Now, with only bi-molecular processing this means for the Load-operation to attach prior the information donor (template) - typically a micro-controller of the same kinship, read out a specific instruction from a specific location in the genome (program) and store this value in the local accumulator (ACCU). Following this, the template-molecule (micro-controller) has to be released and a new micro-controller, preferably not from the same kinship, has to be attached and the value of the ACCU be stored into a specific location of the destination genome (program, prey). This means for each single instruction to be copied, two attachment processes have to be made - reliably. Of course, with any attachment event a completely different micro-controller could be attached, destroying the synchronization between template and offspring. Not using the double-attachment procedure strongly requires a tri-molecular reaction. Biomolecules must be specially designed to allow for this. For the replication of a full program, e.g. with 50 instructions, the pointers of where to read in the foreign instruction and where to write into the other foreign program (prey) have to be maintained. Experiments showed even slight errors with the replication counters made emergence of replication impossible. Usually these counters are realized via registers which are incremented and wrapped around after reaching the end of the template. This requires not only two additional registers which must be addressed, it also requires the incrementing or better decrementing of the values in these registers. Counter operations require pretty expensive Boolean hardware (typically done with arithmetic instructions). All these instructions and addresses require many bits with the according explosion of the search space. The only solution to this coding-dilemma is to assume that the micro-controllers somehow do have physical contact when attached and that one processor is sliding along the other during the copy- process. This sliding, well known in protein-chemistry, makes complex counter arithmetic superfluous. In the current model sliding is realized with an auto-increment feature. After reading (Load) a value from a foreign program the read-counter is incremented automatically, the same holds for write-operations (Store). Each micro-controller has "physically realized" the Load- and Store-counters. These counters are initialized with a value of zero. They might as well be preset randomly or by the position of the recognition-site. These two options are currently not studied because preliminary experiments showed a drastic decrease of the emergence-probability for stable replication.

Two-bit or quaternary encoding

The canonical encoding of instructions in micro-controllers takes 4, 8, 16 or 32 bits per instruction. In a Harvard architecture, especially with 8 and more bits, controllers register-addresses are a fixed part of the bits available. In principle, the register width might be arbitrary. But it is feasible if one register, as well as the accumulator, can be preset by one instruction, otherwise, many instructions must be sequentially executed, with appropriate counters set accordingly. Because of this problem the instruction-structure used here is divided into three parts, the cargo-part (magenta), a special-instruction part (SP, green) and a conditional part (C, orange), see figure . A structural problem is apparent: if the program wants to write a full instruction into a neighboring micro-controller the width of the cargo-part has to be the instruction-width. This of course is only possible if the register width is of instruction-width size but then a register cannot be preset by one single SetAccu-instruction. The only solution to this problem is a sub-coding of a full instruction. In principle, blocking an instruction can be chosen freely. Bit-wise or two-bit-wise encoding is a natural choice here. Because of nature using a quaternary encoding (AUGC-alphabet with RNA) and the work of [15] who showed that the quaternary encoding has the best evolutionary properties we have chosen to encode an instruction with blocks of two-bits each. This means copy-operations which are the combined action of Load- and Store-instructions copy only blocks of two-bits per operation. The consequence is that a full genome copy in the simplest case takes 3*n copy-operations with length n of the genome or program to be copied and 6-bit instruction width, see table 1.

Dissociation or detachment and loops

In origin of life studies the major problem after copying a sequence is the dissociation of the product from the template, also called product inhibition [43]. This also is a problem in the model presented here because there is no obvious choice on what to do after copying is finished. Only a continuous copying and wrapping around after the End-instruction results in the emergence of stable replication systems. The maximum program length currently is 128 quaternary blocks with a maximum program length 42 instructions in the 6-bit case. The copying loop can either be realized via recursively calling a sub-program or via a Goto-instruction. In the case of an infinite long loop the acting micro-controller runs out of energy, reaches a maximum age or is overwritten by another micro-controller. Energy and age parameters are useful knobs to adjust the dynamics of the whole system.

2.3.7  Registers and special registers

Micro-controllers have and do require registers. The question is how many and for what purpose. When trying to emulate biochemistry or molecular biology registers provide a real problem. There is no easy mapping from a storage-place like a register towards an equivalent molecule. For example, a one-bit-register could be realized via a conformation change of a biomolecule, e.g. two different secondary structures of an RNA-molecule due to some reversible chemical modification, for example a disulphide-bridge. Hybridization of co-factors also can mimic such register accesses. Because of this difficulty the number of registers used by the micro-controllers must be as small as possible. We have already seen that we were forced to introduce two further registers to avoid lengthy and improbable pointer arithmetic during the copying process. It is also obvious that we need an accumulator, somewhere we have to store the intermediate values from the template-program. The problem of accessing foreign micro-controllers is solved here by defining the register address 0 or 1 as the access to the program of the attached micro-controllers when reading (Load) from, or writing (Store) into, the attached micro-controller. Furthermore a status-register, see table 4, is defined. The instruction pointer as such is a register which again is subsumed in the physics of the system. The register-address is used for the recognition-procedure, with prepending Site-instructions for specific registers. If the micro-controller's accumulator which serves as a register for another micro-controller is processed independently the register value is probably changed. On the other hand, this register value can be used for communication also, e.g. a micro-controller simply could run in an infinite loop and looking for specific accumulator values in foreign micro-controllers. Complex communication networks can be realized with this setup.

Conditional execution, communication and sensing the environment

The conditional-part (C), is currently two bits wide. This coding was chosen because conditional execution is powerful and avoids the need of several instructions to code for conditional expressions. Two types of instructions exists: instructions are always executed and instructions are subjected to a conditional evaluation, see table 3. High-level communication between micro-controllers is not only realized using other micro-controllers as registers, but also utilizing the PF1-flag, see table 4. Additionally, indirect communication can be realized by setting other bits of the partner machine's status register. The value of the accumulator is mapped into the status-register of the attached micro-controller. Affected is the micro-controller which is available after a read-instruction (Load). Please note, this read-instruction has as a side-effect: the increment of the read-counter. The PF1-flag is the only flag which can be sensed directly by the executed program, see table 3. Providing the system from the outside with additional information is done by issuing the PF1-flag of specific micro-controllers, for example with a pixel-value of a black-and-white image. Output of the system can be realized in the same way, simply look at the PF1-flags of other specific micro-controllers or their accumulator values. With this procedure arbitrary communication networks can be evolved and trained. Furthermore, this output could be utilized to specify the hardware of micro-controllers, important in questions of hardware-evolution.

2.3.9  Codon mapping

Reading and writing to other machines can be subjected to a codon-mapping - resembling the Watson-Crick pairing in biology. A special option of the simulation program allows to specify the mapping used. The identity-mapping has the value \mathnormalc=0xe4 (\mathnormal11 10 01 00) assuming a quaternary coding scheme. Thus a value \mathnormali=0x2 is mapped to \mathnormala=0x2 with a=((c >> (i*2))Ù0x3). With a mapping table \mathnormalc=0x53 the value \mathnormali=0x2 is mapped to \mathnormala=0x1. If the mapping table creates a complementary mapping (e.g. \mathnormalc=0xb1) a second application of the mapping brings back the old starting value. The cycle length is exactly one. According to the maximum length sequence (MLS) theory [21, 9], the maximum cycle-length of a quaternary mapping can be 2²-1=3. For example with \mathnormalc=0x4b (0,1,2,3)->(3,2,0,1)->(1,0,3,2)->(2,3,1,0)->(0,1,2,3) a cycle of length three is realized. With these mapping-tables even unnatural translations can be tested for their evolutionary properties. The experiments reported in this work all have been done with the identity-mapping \mathnormalc=0xe4. With the condition that there exists always a mapping to each possible codon two classes of mappings, apart from the identity-mapping, remain: Class A is of the Watson-Crick pair type \mathnormalc=0xb1 - after two steps the starting point is back again and Class B cycles through the full space of possible codons. Class A has three members with c={0x1b, 0x4e, 0xb1} and a Class B comprises six members with c={0x1e, 0x39, 0x4b, 0x72, 0x8d, 0x93}. With the identity-mapping \mathnormalc=0xe4 three possible evolutionary mapping-types are possible. A hypothesis is that the evolutionary behavior in between the classes will not change, though there might be peculiar interactions between the mappings in a class and the particular instruction-set. All other possible mappings restrict the codon-space and allow only a subset of codons to be executed in a usual way. Of course, it might be that through mutations non-reachable codons by chance still come into play. The identity-mapping for a binary-base (only 0 and 1 as base) is \mathnormalc=0x2 and an eighth-base-system (3 bits per base) is \mathnormalc=0xfac688. Preliminary experiments with Watson-Crick-type mappings so far did not reveal viable replication systems.

Energy management in the system

The distribution of energy must be organized such that at least a very small number of micro-controllers can survive without doing something special. Additionally, energy should be distributed according to given external objectives. The natural choice would be the PF1-flag as the sensor for external input. A set of dedicated accumulators can serve as output-channels. A first simple task to be performed might be the counting of set PF1-flags and write the result into an output-register. The amount of energy distributed per container would then be proportional to the correctness of the output. In the experiments reported energy was not subjected to some external tasks. *  Six parameters for the simulations with energy-processing are defined:

_OPT_TOTAL_ENERGY_

(-te #i) The total energy provided by the environment per generation and container. This energy is delivered to each living or newly instantiated micro-controller.

_OPT_DEATH_ENERGY_

(-de #i) A micro-controller which energy-resources drop below this threshold is interpreted as dead. Dead means that the micro-controller does not get CPU-time for execution. The program of the micro-controller instead remains intact as a type of crystal, meaning the information in the program will be conserved (as long as not an external mutation or rewriting event changed this information). Not only the information of the micro-controller remains intact, also the content of the accumulator is still accessible via others. The rational is the argument that the energy to access the accumulator of the dead micro-controller is already provided by the acting micro-controller.

_OPT_EARN_ENERGY_

(-ee #i) The amount of energy which can be earned when doing a successful operation. An operation is defined as an action which somehow connects the micro-controller to the outside world. Thus, success is defined from the outside of the simulation and either part of the physics in the system or some external task to be solved. In the experiments reported this value remained constant throughout the simulation.

_OPT_SPENT_ENERGY_

(-se #i) Energy to be spent for each executed instruction. It is possible to separate the real energy costs per specific instruction by coefficients. E.g., a register-access might be much more expensive than a SetFA-operation, and calling another micro-controller as a subroutine is energetically certainly different from attaching a different micro-controller.

_OPT_PROG_ENERGY_

(-pe #i) Energy to be spent for each program execution. The reason is the freedom of micro-controllers to do nothing and never going to die because simply surviving by the background-energy. With this cost high enough these parasitic micro-controllers will die and be replaced by new micro-controllers.

_OPT_MIN_MICROS_

(-mm #i) This is the minimum number of micro-controllers living at the beginning of a new generation. If less than the minimum number of living micro-controllers are in a container, dead micro-controllers are picked at random and reinitialized with the energy reservoir set to the total amount of energy. With reinitialization the accumulator value is set to the initial value and the program is preset with default values, e.g. random values. No former state of the micro-controller is maintained. The only exception is in the beginning of the simulation: then each micro-controller gets a starting energy. The reason is that starting with a totally randomized population will yield most of the micro-controllers dead after the first generation.

_OPT_GRAB_ENERGY_

(-ge #) This is an anergy packet which can be grabbed by a micro-controller. This micro-controller finds a prey in its environment either specific or unspecific. The number of energy packets allocarted is defined in the cargo-part.

_OPT_MOVE_ENERGY_

(-me #) Energy spent for one moving step, see instruction Move

Several different energy coefficients have been tested but none of them systematically. It turned out that more or less neutral coefficients are most suited for evolutionary purposes.

Introducing variable length programs

Variable length programs are even more akin to physico-chemical systems found in nature. They immediately require operators utilizing length dynamics of the informational sequences. The first two most obvious operators are Ligation and Splitting, see table 7. But there are subtle problems or features as well: e.g. when does copying stop? With fixed-length programs copying was stopped after encountering the End-instruction. It simply did not make sense to waste CPU-time and also copy the rest of the program. In the same way it was feasible to overwrite the program of the prey without taking into account what was written in the prey's program before. With variable sequence-lengths instead the situation changes. Sequences are now seen as physical molecules which are to be copied. Copying itself becomes a construction process, not a replacement process, as in the former case, and thus the length of the prey's program is changed with the copying process. For example, this requires the adjustment of the instruction-pointer of this machine because after copying the prey might have shrunken and the pointer is addressing illegal memory locations. The dynamics with variable length sequences alter, data not shown, even providing replicative sequences at instantiation time only yield extremely bad proliferation and high sensitivity to parasites.

Execute	S0	S1	S2	S3
J0	SetAccu	Site	Load	Store
J1	Action	Call	SetFA	SetFB
J2 (ZF)	"	"	"	"
J3 (PF1)	"	"	"	"

Table 6: Instructions available when variable program lengths are used. This it the right part of table 1. The End/Cycle instruction has be replaced by the instruction Action. Depending on the bits provided by the cargo-part certain actions are executed. All defined actions are specified in table 7. The instruction SetAccu took the place of the former End/Cycle-instruction. Please look at the symmetry of the instructions. SetAccu and Site are accessible with a machine-mask of 0x1. Machine-mask 0x3 adds the instructions Load and Store which empower the machine to copy other programs. Machine-mask 0x7 (0xb when three bits are used for the special command (SP)) further adds two procedural commands Action and Call and two property changing commands SetFA and SetFB. Variable sequence lengths also revealed a further problem for the emergence of replicative systems. It turned out that very short, typically one instruction long sequences with a single Site-instruction occurred as targets for the replicating machines. Because of being extremely short these sequences easily could outperform the machines with a valid replication program. With a simple and biologically plausible trick this problem could be mitigated. Only sequences with a length of at least three instructions can partake at binding. Sequences shorter than this are not considered in specific binding though they still can be bound unspecifically as preys of the replication process.

Action	Description
Ligate (00)	If there are two machines located, one in the reading and another in the writing-slot, the program of the machine in the writing slot is appended to the program in the reading-slot. The machine in the writing slot is invalidated after that and will be replaced by a newly created machine at the next simulation round.
Split (01)	If there are two machines located in the reading and writing-slot the program of the machine in the writing slot is replaced by the program right after the current remote instruction pointer (typically after the recognition site). The program in the reading slot is shortened accordingly.
CopyMask (10)	Copy the machine-mask from the reading-slot-machine into the machine's machine-mask attached at the writing-slot.
CopyLen (11)	Copy the length of the machine in the reading-slot into the machine of the writing-slot, which resembles a truncation or an elongation.
Release reading-slot (100)	If a machine is attached at the reading-slot it will be released via this action.
Release writing-slot (101)	If a machine is attached at the writing-slot it will be released via this action.

Table 7: Possible action-commands. Depending on the number of bits in the cargo-part of the instruction, see Figure , the shown actions can take place. An additional problem occured with the emergence of replicators. Looking at the evolving programs revealed that many codes with a length of only one instruction occured utilizing most of the CPU-time, see above on the minimum template length. Especially when these programs consisted of one Store-instruction neighboring machines could be overwritten with a single value independent of what useful functionality had been evolved before. This sort of denial of service or vandalism in the system made the emergence of replicative systems impossible. With a minimum program length of two instructions this problem is no longer existent. It is biologically plausible to require a certain minimum complexity or length of sequences before emergent replication can occur. This gives a lower bound of the length of nucleotides considered in biochemical origin-of-life experiments.

Different types of micro-controllers

Execute S0 S1 S2 S3 J0 SetAccu Site Load Store J1 Action Call SetFA SetFB J2 (ZF) " " " " J3 (PF1) " " " "

S4 S5 S6 S7 Nand SL SR Goto GetFA GetFB Decr RND " " " " " " " "

Table 8: Instruction set used with three bits in the special-commands part (SP). The possible flags are described in table 4. The default instruction for (J0:S0) is Cycle. This instruction lets the instruction pointer jump to address zero. The instruction (J0:S0) can be changed by clearing the _CYCLE_-flag with the SetFB instruction.

Acronym	Description
Nand	Calculate a Boolean NAND function of the accumulator and the register address with the cargo-part. The result is stored in the accumulator. Prepending Site-instructions increase the specificity of the register-addressing.
Goto	Continue the execution at program address given with the cargo-part of the instruction.
SL, SR	Shift ACCU left (right) cyclically.
GetFA	Get flags of foreign micro-controller which is located in reading-slot. If no micro-controller available accumulator is not changed.
GetFB	Get my own flags and store them in the accumulator.
Decr	Decrement the accumulator. If zero, wrap around to the maximum accumulator value.
RND	Fill the accumulator with a random value.

Table 9: Eight further commands can be coded with a third bit available for the special command section (SP). See table 2 for the other possible instructions. Before delving into the area of hardware-evolution, an intermediate step can be investigated: allowing different types of machines to participate in the evolutionary course. The special-command part (SP) in figure was extended from two to three bits. This means an instruction with a cargo-width of two bits is then seven bits wide. See tables 2 and 9 for the additional instructions available. To simulate now a machine with only six-bits of instruction-width the one added bit in the special-part of the instruction is simply masked out. A special property of a machine, the machine-mask, was introduced. This masking procedure in addition allows to simulate a three-bits instruction-width machine, which of course with two possible instructions is not able to evolve something (End and Site in the fixed program length scenario, or SetAccu and Site in the variable length scenario, see table 1). But with four bits width Load and Store become part of the instruction set and a replicating systems can evolve. With these machines (machine-mask is 0x3) 12 bits are needed for the minimal replication program, see 5 (right part). Experiments could show that the emergence of replicating systems was considerably easier in this case. Even with a machine-mask of 0x7 evolution starts more or less right from the beginning. The only drawback is that these machines are no longer universal. The interesting question arises is there an evolutionary pathway from simple machines to complex machines possible when the machine-mask is subjected to evolution.

Interactions and more physics

Currently the physics of the programs as such is a one-dimensional string of instructions, once formed, being strict and rigid. This rigidity can be changed by looking at these programs as pools of molecules (one molecule resembles one instruction) and these molecules somehow attached to each other via specific bonds. These bonds can be strong and unbreakable meaning forming a rigid string of instructions which is processed from beginning to the end. On the other hand the bonds can be extremely weak or even absent such that processing of the machine would result in a more or less randomized sequence of execution of the instructions. In between all flavours and variants of bond can be envisioned. In a first approximation each of these instructions is thought to have two connection sites, allowing the formation of linear strings only. The degree of freedom then available is the affinity of forming bonds between the various instructions. An affinity-matrix can be defined which tells the system how likely a bond between to instructions is going to be formed. Primitive operators in the physical environment can work on these bonds, exchanging elements or even breaking or creating bonds. This means an existing bond determines with its corresponding value in the affinity-matrix whether during execution the following instruction is executed or a randomly chosen other instruction of the program. Also the primitive operators obey the affinity-matrix when working on pairs of instructions. In addition to the primitive bond-forming and breaking-operators other machines have access to bonds and also could be able to change the affinity-matrix. This is a natural choice because instructions are no atom, in reality they are expected to be more or less complex agglomerations of either nucleotides, peptides or other organic molecules which certainly are subjected to the operations of other enzyme-like catalysts.

Execute S8 S9 S10 S11 J0 SetXA SetYA LoadA StoreA J1 GrabE Move FastM Drag J2 (ZF) " " " " J3 (PF1) " " " "

S12 S13 S14 S15 SetXT SetYT LoadT StoreT RMove Strans - - " " " " " " " "

Table 10: Instruction set used with three bits in the special-commands part (SP). The possible flags are described in table 4. The default instruction for (J0:S0) is Cycle. This instruction lets the instruction pointer jump to address zero. The instruction (J0:S0) can be changed by clearing the _CYCLE_-flag with the SetFB instruction.

Acronym	Description
SetXA	Set the x-coordinate of the affinity matrix. Accessing the affinity-matrix the next time is done at this given x-coordinate.
SetYA	Set the y-coordinate of the affinity matrix. Accessing the affinity-matrix the next time is done at this given y-coordinate.
LoadA	Load the current value of the affinity matrix into the accumulator. The coordinate has been specified before by the SetXA and SetYA instructions.
StoreA	Store the current accumulator into the affinity-matrix. The coordinate has been specified before by the SetXA and SetYA instructions.
GrabE	Grab quantums of energy from a neighboring micro-controller. The size of the energy-quantum is defined via the coefficient _STAT_GRAB_ENE_. The number of energy-packets grabbed is given by the cargo-load.
Move	Move the micro-controller to the next container. This is an active move. The energy spent for moving is defined by the coefficient _STAT_MOVE_ENE_. The direction of move is defined via the cargo-load. In a one-dimensional system bit 0 of the cargo specifies whether the micro-controllers moves to the next container (con_id + 1, bit0 = 1) or to the previous container (con_id - 1, bit0 = 0). In a two-dimensional system bit1 defines the y-direction of the move.
FastM	Fast move of the micro-controller to the next n-th container. This is an active move. The energy spent for moving is defined by the coefficient _STAT_MOVE_ENE_ times two times n the energy. The direction of the fast move is defined via the cargo-load. See Move instruction for the direction.
Drag	Same as Move with the exception that the attached micro-controllers are moved as well. The energy costs are as in the Move-instruction. Each dragged micro-controller costs the same amount of energy which is taken from the dragging micro-controller.

Acronym	Description
SetXT	Define the x-coordinate of the translation table
SetYT	Define the y-coordinate of the translation table
LoadT	Load a value from the translation table (coordinate XYT)
StoreT	Store a value into the translation table (coordinate XYT)
RMove	Move k-containers into a random direction. The value k steems from the accumlator.
STrans	Switch the active translation table

The translation table   Objective of the translation table is to allow a secondary structure mapping system to be simulated. The raw bits are mapped into certain instructions bits. The active mapping table can be chosen with the instruction STrans.