The left schematic process flow illustrates the fabrication process for the electrode layer of the BioMEMS-Chip which we have enhanced in cooperation with the technical team of the center of advanced european studies and research (caesar) Bonn, Germany. A 6-inch wafer provides the electrical layer for 16 FPFAs. The process flow starts with a two lithographic steps for embedding and structuring the metal layer containing the electrodes, wires and contact pads. The following step is a Plasma Enhanced Chemical vapour deposition (PECVD) of silicon oxide (SiO2) passivation layer. After opening the passivation layer at the electrode and conducting pad areas, 18 fluidic I/O holes (Diameter 300 µm) were placed using deep etching by Inductively Coupled Plasma (ICP) to allow a reverse side fluidic connector to be used.
The dimensions of the resulting silicon chip (upper images) are 28 x 32 mm and supports lithographically structured gold wires leading individually from a multitude of microelectrode-arrays to ball-grid connector pads for a FPGA and to an external connector. The microelectrodes have dimensions from 10 to 40 µm in width and up to 200 µm in length with spacing of 10 to 200 µm. This primarily design of the chip contained 288 single controllable microelectrodes.